Japanese Patent Application Publication No. 2001-250947 (hereinafter referred to as Patent Document 1) discloses an insulated gate bipolar transistor (IGBT) including an n-base layer, a p-base layer, an n-emitter layer, and a gate electrode. The p-base layer includes a high-density p-base layer in which a p-type impurity density is high, and a low-density p-base layer in which a p-type impurity density is low. The high-density p-base layer is in contact with the n-base layer, and the low-density p-base layer is in contact with the n-emitter layer. When an on-potential is applied to the gate electrode, a channel is formed in the p-base layer, whereby electrons flow from the n-base layer toward the n-emitter layer. In the IGBT, when a voltage between a collector and an emitter becomes larger, a potential of the high-density p-base layer is increased, and the channel formed in the high-density p-base layer is pinched off, thus saturating current flowing through the IGBT. Thus, the IGBT has a high short circuit tolerance. Note that although Patent Document 1 describes a technique for providing the high-density p-base layer in the IGBT, the provision of a high-density p-base layer in other insulated gate type switching devices, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), can also improve the short circuit tolerance.